Computer Architecture I
A.Y. 2022/2023
Learning objectives
The course introduces the principles at the base of a computer; simple logic gates are first presented, and then combined, thought a succession of intermediate abstraction layers, into the design of ALU firmware and of a MIPS architecture, capable of executing programs with a core machine language.
Expected learning outcomes
The student will be familiar with the basic principles underlying the processing of digital information. In particular, (s)he will have the skills needed to understand, analyze and design
combinatorial and sequential circuits.
combinatorial and sequential circuits.
Lesson period: First semester
Assessment methods: Esame
Assessment result: voto verbalizzato in trentesimi
Single course
This course cannot be attended as a single course. Please check our list of single courses to find the ones available for enrolment.
Course syllabus and organization
Edition 1
Responsible
Lesson period
First semester
Course syllabus
THEORY
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
[Program for not attending students with reference to descriptor 1 and 2]:
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
LABORATORY
Design and realization of logical circuits through a simulator.
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
Design and realization of logical circuits through a simulator.
[Program for not attending students with reference to descriptor 1 and 2]:
Introduction
The reference architecture. The execution cycle of an instruction. History of the computer. How to code the information. Binary representation of digital numbers.
Combinatorial logic and algebra
Operations on binary numbers. The fundamental operations: addition and subtraction. Binary representation of floating point numbers. Combinatorial logic. Boole algebra: variables and operators. Circuital implementation (logical gates). From circuit to function. Universal gates. From functions to circuits. The truth tables. From truth tables to circuits: the first canonic form. Implementation of logical functions in PLAs or ROMs. Noticible combinatorial circuits. Exercises.
Arithmetic-logical units
Adder. The carry problem. Hardware multipliers. Design of an ALU with two stages. Adder on 32 bits. Support to the comparison operations. Carry ahead. Introduction to firmware. Firmware circuits for multiplication and division. Arithmetics and adders for floating point numbers.
Sequential logic
Temporization of boolean circuits. Sequential circuits. Transition tables. Eccitation tables. The latch SC and the latch D. Registers and the Register file. Temporization problems. The flip-flops. Finite state machines. From specifications to the project. The state transition graph and the state transition table. Coding the STT. Synthesis of the circuit of a finite state machine. Examples.
Introduction to CPU
A simple CPU and its control unit. Instruction format. Introduction on assembly language and machine code.
LABORATORY
Design and realization of logical circuits through a simulator.
Prerequisites for admission
None.
Teaching methods
a) Frontal lessons + b) Laboratory on the subject. Attending lessons and laboratory is strong advised.
Teaching Resources
Basic text for Computer Architecture courses I and II (available in both English and Italian):
· ""Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
· ""Computer Organization & Design: The Hardware/Software Interface", D.A. Patterson and J.L. Hennessy, Morgan Kaufmann Publishers, Sixth Edition, 2020. NB Morgan Kaufman also published a version of the text for RISC-V and for ARM, not adopted in this course.
Assessment methods and Criteria
The evaluation is performed through a written exam followed by an oral exam and a laboratory test.
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
For the laboratory part, the exam is written and lasts two hours: the student has to solve on a PC some given exercises. Each exercise deals with building a digital circuit according to given specifications. The exam lasts 1 hour and the student can use didattic material approved by the teacher.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
The written exam and the laboratory exam can be sustained in different rounds, but inside a time span no longer than 6 months or
three consecutive rounds (the least restrictive applies).
In the written exam, that lasts three hours, the student has to solve exercises that required to apply the concepts learnt in the course and to answer to some open questions. The oral exam is based on the discussion on what had been produced in the written exam and on questions related to the program.
For the laboratory part, the exam is written and lasts two hours: the student has to solve on a PC some given exercises. Each exercise deals with building a digital circuit according to given specifications. The exam lasts 1 hour and the student can use didattic material approved by the teacher.
Each exam is evaluated in thirtieth and final evaluation is the average of the score assigned to the three exams.
In all three exams, evaluation takes into consideration the level and depth of knowledge and the clarity of language.
The written exam and the laboratory exam can be sustained in different rounds, but inside a time span no longer than 6 months or
three consecutive rounds (the least restrictive applies).
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Professors:
Borghese Nunzio Alberto, Trucco Gabriella
Shifts:
Professor:
Borghese Nunzio Alberto
Turno A
Professor:
Trucco GabriellaEdition 2
Responsible
Lesson period
First semester
Course syllabus
For the theory part:
- introduction to the course topics, objectives, and organization;
- representation and logical processing of information: binary representation for natural, integer, and real numbers, binary functions, and Boolean algebra;
- physical representation and processing of information: logic gates and truth tables;
- synthesis of binary functions with combinational circuits, building an arithmetic-logic unit (ALU);
- storing information: sequential logic elements (bistable, latch, clock synchronization);
- synthesis of sequential circuits, finite state machines;
- design of a single-cycle CPU and outline of the multi-cycle case;
For the laboratory part, besides an introductory tutorial on the adopted software tools, sessions will cover:
- binary coding;
- combinatorial logic (canonical forms, critical path);
- advanced combinatorial logic (multiplication, ALU);
- sequential logic (Memories, finite state machines);
The theory and laboratory parts are carried out in parallel. The beginning of the lab sessions is usually delayed of one/two weeks.
- introduction to the course topics, objectives, and organization;
- representation and logical processing of information: binary representation for natural, integer, and real numbers, binary functions, and Boolean algebra;
- physical representation and processing of information: logic gates and truth tables;
- synthesis of binary functions with combinational circuits, building an arithmetic-logic unit (ALU);
- storing information: sequential logic elements (bistable, latch, clock synchronization);
- synthesis of sequential circuits, finite state machines;
- design of a single-cycle CPU and outline of the multi-cycle case;
For the laboratory part, besides an introductory tutorial on the adopted software tools, sessions will cover:
- binary coding;
- combinatorial logic (canonical forms, critical path);
- advanced combinatorial logic (multiplication, ALU);
- sequential logic (Memories, finite state machines);
The theory and laboratory parts are carried out in parallel. The beginning of the lab sessions is usually delayed of one/two weeks.
Prerequisites for admission
None.
Teaching methods
The theory part is given with frontal lectures where slides are presented. Slides are made available in PDF format through the Ariel platform.
The laboratory part proposes guided exercising sessions at the PC. The adopted software tools and the exercises (instructions and selected solutions) are made available through the Ariel platform.
Attendance is recommended for both the theory and the laboratory part.
The laboratory part proposes guided exercising sessions at the PC. The adopted software tools and the exercises (instructions and selected solutions) are made available through the Ariel platform.
Attendance is recommended for both the theory and the laboratory part.
Teaching Resources
Course website on the Ariel platform: https://nbasilicoae1.ariel.ctu.unimi.it/
Slides, exercises, and other supplementary materials will be provided.
Both the theory and the laboratory part are based on the topics covered in: "Computer Organization & Design: The Hardware/Software Interface" by David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers.
Slides, exercises, and other supplementary materials will be provided.
Both the theory and the laboratory part are based on the topics covered in: "Computer Organization & Design: The Hardware/Software Interface" by David A. Patterson and John L. Hennessy, Morgan Kaufmann Publishers.
Assessment methods and Criteria
For the theory part, there will be a written test lasting 3 hours at most where the resolution of an adequate number of exercises is proposed. Each exercise involves the application of the principles and techniques presented during the lectures. During the exam, consulting any material is forbidden.
For the laboratory part, the exam consists of carrying out some proposed exercises on the PC and lasts about 1 hour. Each exercise involves the construction of a digital circuit according to specific functional requirements. During the exam, specific material approved by the teacher can be consulted.
Both tests, theory, and laboratory result in a grade out of thirty which is communicated through the Ariel platform (optionally also by email). If both grades are greater than or equal to 18, the exam is passed with a grade equal to the weighted average of the theory grade (weight 2/3) and the laboratory grade (weight 1/3). The two tests can be passed in different exam sessions but in a time span of at most 6 months or three successive exam sessions (choosing the less restrictive of the two).
The assessments will take into account: confidence in applying techniques, correctness, and elegance of the solutions, clarity of presentation. The tests and their assessments will not be differentiated on the basis of attendance.
For the laboratory part, the exam consists of carrying out some proposed exercises on the PC and lasts about 1 hour. Each exercise involves the construction of a digital circuit according to specific functional requirements. During the exam, specific material approved by the teacher can be consulted.
Both tests, theory, and laboratory result in a grade out of thirty which is communicated through the Ariel platform (optionally also by email). If both grades are greater than or equal to 18, the exam is passed with a grade equal to the weighted average of the theory grade (weight 2/3) and the laboratory grade (weight 1/3). The two tests can be passed in different exam sessions but in a time span of at most 6 months or three successive exam sessions (choosing the less restrictive of the two).
The assessments will take into account: confidence in applying techniques, correctness, and elegance of the solutions, clarity of presentation. The tests and their assessments will not be differentiated on the basis of attendance.
INF/01 - INFORMATICS - University credits: 6
Laboratories: 24 hours
Lessons: 36 hours
Lessons: 36 hours
Shifts:
Professor:
Basilico Nicola
Turno B
Professor:
Rivolta Massimo WalterTurno C
Professor:
Re' MatteoProfessor(s)